IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
Year	Cited Authors	Cited Work	Volume
1992	Ramirezangulo J, Robinson M, Sanchezsinencio E	Current-Mode Continuous-Time Filters - 2 Design Approaches	39 (6): 337-341
1992	Georgiou GM, Koutsougeras C	Complex-Domain Backpropagation	39 (5): 330-334
1992	Leung BH, Sutarja S	Multibit Sigma-Delta A/D Converter Incorporating A Novel Class Of Dynamic Element Matching Techniques	39 (1): 35-51
1992	Chao TH, Hsu YC, Ho JM, Boese KD, Kahng AB	Zero Skew Clock Routing With Minimum Wirelength	39 (11): 799-814
1992	Constantinides	Lagrange Programming Neural Networks	39 (7): 441-452
1992	Elleithy KM, Bayoumi MA	Fast And Flexible Architectures For RNS Arithmetic Decoding	39 (4): 226-235
1992	Chen CK, Lee JH	Design Of Quadrature Mirror Filters With Linear-Phase In The Frequency-Domain	39 (9): 593-605
1993	Cuomo KM, Oppenheim AV, Strogatz SH	Synchronization Of Lorenz-Based Chaotic Circuits With Applications To Communications	40 (10): 626-633
1993	Roska T, Chua LO	The CNN Universal Machine - An Analogic Array Computer	40 (3): 163-173
1993	Dedieu H, Kennedy MP, Hasler M	Chaos Shift Keying - Modulation And Demodulation Of A Chaotic Carrier Using Self-Synchronizing Chua Circuits	40 (10): 634-642
1993	Schreier R	An Empirical-Study Of High-Order Single-Bit Delta-Sigma Modulators	40 (8): 461-466
1993	Frey DR	Chaotic Digital Encoding - An Approach To Secure Communication	40 (10): 660-666
1993	Ra SW, Kim JK	A Fast Mean-Distance-Ordered Partial Codebook Search Algorithm For Image Vector Quantization	40 (9): 576-579
1993	Cruz JM, Chua LO	An IC Chip Of Chua's Circuit	40 (10): 614-625
1993	Carroll TL, Pecora LM	Synchronizing Nonautonomous Chaotic Circuits	40 (10): 646-650
1993	Rodriguezvazquez A, Espejo S, Dominguezcastro R, Huertas JL, Sanchezsinencio E	Current-Mode Techniques For The Implementation Of Continuous-Time And Discrete-Time Cellular Neural Networks	40 (3): 132-146
1993	Rodriguezvazquez A, Delgadorestituto M	CMOS Design Of Chaotic Oscillators Using State Variables: A Monolithic Chua's Circuit	40 (10): 596-613
1993	Crounse KR, Roska T, Chua LO	Image Half-Toning With Cellular Neural Networks	40 (4): 267-283
1993	Lim YC, Lian Y	The Optimum Design Of One-Dimensional And 2-Dimensional FIR Filters Using The Frequency-Response Masking Technique	40 (2): 88-95
1993	Abarbanel HDI, Linsay PS	Secure Communications And Unstable Periodic-Orbits Of Strange Attractors	40 (10): 643-645
1993	Cho NI, Lee SU	On The Adaptive Lattice Notch Filter For The Detection Of Sinusoids	40 (7): 405-416
1993	Meyer MD, Agrawal DP	A High Sampling Rate Delayed LMS Filter Architecture	40 (11): 727-729
1993	Liu DR, Michel AN	Cellular Neural Networks For Associative Memories	40 (2): 119-121
1993	Shanbhag NR, Parhi KK	Relaxed Look-Ahead Pipelined LMS Adaptive Filters And Their Application To ADPCM Coder	40 (12): 753-766
1994	Lang M, Laakso TI	Simple And Robust Method For The Design Of Allpass Filters Using Least-Squares Phase Error Criterion	41 (1): 40-48
1994	Ramirezangulo J, Sanchezsinencio E	High-Frequency Compensated Current-Mode Ladder Filters Using Multiple-Output OTAs	41 (9): 581-586
1994	Rioul O, Duhamel P	A Remez Exchange Algorithm For Orthonormal Wavelets	41 (8): 550-560
1994	Liu D, Michel AN	Sparsely Interconnected Neural Networks For Associative Memories With Applications To Cellular Neural Networks	41 (4): 295-307
1994	Gao KQ, Ahmad MO, Swamy MNS	A Constrained Anti-Hebbian Learning Algorithm For Total Least-Squares Estimation With Applications To Adaptive FIR And IIR Filtering	41 (11): 718-729
1995	Vishwanath M, Owens RM, Irwin MJ	VLSI Architectures For The Discrete Wavelet Transform	42 (5): 305-316
1995	Baird RT, Fiez TS	Linearity enhancement of multibit Delta Sigma and D/A converters using data weighted averaging	42 (12): 753-762
1995	Dempster AG, Macleod MD	Use Of Minimum-Adder Multiplier Blocks In FIR Digital-Filters	42 (9): 569-577
1995	Harjani R	A Low-Power CMOS VGA For 50 MB/S Disk-Drive Read Channels	42 (6): 370-376
1995	Craninckx J, Steyaert M	Low-noise voltage-controlled oscillators using enhanced LC-tanks	42 (12): 794-804
1995	Karam LJ, Mcclellan JH	Complex Chebyshev-Approximation For FIR Filter Design	42 (3): 207-216
1995	Tsividis Y	On Linear Integrators And Differiantiators Using Instantaneous Companding	42 (8): 561-564
1995	Toner MF, Roberts GW	A Bist Scheme For A SNR, Gain Tracking, And Frequency-Response Test Of A Sigma-Delta ADC	42 (1): 1-15
1995	Herley C	Boundary Filters For Finite-Length Signals And Time-Varying Filter Banks	42 (2): 102-114
1996	Yin L, Yang RK, Gabbouj M, Neuvo Y	Weighted median filters: A tutorial	43 (3): 157-192
1996	Hartley RI	Subexpression sharing in filters using canonic signed digit multipliers	43 (10): 677-688
1996	Elwan HO, Soliman AM	A novel CMOS current conveyor realization with an electronically tunable current mode filter suitable for VLSI	43 (9): 663-670
1996	Perry D, Roberts GW	The design of log-domain filters based on the operational simulation of LC ladders	43 (11): 763-774
1996	Kocarev L, Wu CW, Chua LO	Complex behavior in digital filters with overflow nonlinearity: Analytical results	43 (3): 234-246
1996	Smith SL, SanchezSinencio E	Low voltage integrators for high-frequency CMOS filters using current mode techniques	43 (1): 39-48
1997	Razavi B	Design considerations for direct-conversion receivers	44 (6): 428-435
1997	Tsividis Y	Externally linear, time-invariant systems and their application to companding signal processors	44 (2): 65-85
1997	Galton I	Spectral shaping of circuit errors in digital-to-analog converters	44 (10): 808-817
1997	Kramer J, Sarpeshkar R, Koch C	Pulse-based analog VLSI velocity sensors	44 (2): 86-101
1997	Oklobdzija VG, Maksimovic D, Lin FC	Pass-transistor adiabatic logic using single power-clock supply	44 (10): 842-846
1997	Sankarayya N, Roy K, Bhattacharya D	Algorithms for low power and high speed FIR filter realization using differential coefficients	44 (6): 488-497
1997	Denk TC, Parhi KK	VLSI architectures for lattice structure based orthonormal discrete wavelet transforms	44 (2): 129-132
1998	Crols J, Steyaert MSJ	Low-IF topologies for high-performance analog front ends of fully integrated receivers	45 (3): 269-282
1998	Motamed A, Hwang C, Ismail M	A low-voltage low-power wide-range CMOS variable gain amplifier	45 (7): 800-811
1998	Han G, Sanchez-Sinencio E	CMOS transconductance multipliers: A tutorial	45 (12): 1550-1563
1998	Hardin DP, Roach DW	Multiwavelet prefilters - I: Orthogonal prefilters preserving approximation order p <= 2	45 (8): 1106-1112
1998	Hsu CT, Wu JL	Multiresolution watermarking for digital images	45 (8): 1097-1101
1998	Adler V, Friedman EG	Repeater design to reduce delay and power in resistive interconnect	45 (5): 607-616
1998	Blalock BJ, Allen PE, Rincon-Mora GA	Designing 1-V OP amps using standard digital CMOS technology	45 (7): 769-780
1999	Wang Z, Zhang D	Progressive switching median filter for the removal of impulse noise from highly corrupted images	46 (1): 78-80
1999	Herzel F, Razavi B	A study of oscillator jitter due to supply and substrate noise	46 (1): 56-62
1999	Christen E, Bakalar K	VHDL-AMS - A hardware description language for analog and mixed-signal applications	46 (10): 1263-1272
2000	Koutsoyannopoulos YK, Papananos Y	Systematic analysis and modeling of integrated inductors and transformers in RF IC design	47 (8): 699-713
2000	Boahen KA	Point-to-point connectivity between neuromorphic chips using address events	47 (5): 416-434
2000	Toker A, Ozoguz S, Cicekoglu O, Acar C	Current-mode all-pass filters using current differencing buffered amplifier and a new high-Q bandpass filter configuration	47 (9): 949-954